Xilinx Vitis Core Development Kit + PetaLinux 2021.1

Xilinx Vitis Core Development Kit / PetaLinux

The Vitis unified software platform includes:

  • Comprehensive core development kit to seamlessly build accelerated applications
  • Rich set of hardware-accelerated open-source libraries optimized for Xilinx FPGA and Versal ACAP hardware platforms
  • Plug-in domain-specific development environments enabling development directly in familiar, higher-level frameworks
  • A Growing ecosystem of hardware-accelerated partner libraries and pre-built applications

Xilinx Vitis Core Development Kit

Complete set of graphical and command-line developer tools that include the Vitis compilers, analyzers and debuggers to build, analyze performance bottlenecks and debug accelerated algorithms, developed in C, C++ or OpenCL. Leverage these features within your own IDEs or use the standalone Vitis IDE.

What is new 

ADF: Adaptive Data Flow

  • Compiler:
    • Event tracing on PLIO or GMIO
    • Event tracing also on Hardware
    • Heat Map generation: %utilization of all AI Engines
    • Supports different PL frequencies for PL kernels and PLIOs
  • Vitis IDE for AI Engines
    • Pipeline view
    • Vector register view
    • Internal memory views East, West North, South
    • External memory

Vitis HLS

  • Vitis HLS replaces Vivado HLS in Vivado (it was already default for Vitis and C based kernel compilation in 2020.1)
    • Adds array reshape and partitioning pragmas for top function ports
  • The tool is now installed in its own directory ./Vitis_HLS/2020.2 alongside Vitis and Vivado
  • HLS design migration information has been updated in UG1391
  • Vitis HLS user guide is UG1399, the full content is also available in HTML
  • Updated design examples on GitHub, they can also be loaded automatically from the Vitis HLS GUI (from the “Git Repositories” sub-window) for direct access
  • Support for SIMD programming
  • Support for on-chip block RAM ECC flags via the bind_storage pragma (Vivado flow only) to monitor error correction logic generated by the RAM blocks
  • GUI has a simplified toolbar icon layout, new reporting sections for interfaces and AXI4 including bursts
  • Non-default options can be filtered for quick review in “Solution Settings”→”General” then “Show only non-defaults” tick mark
  • User can create and open a project in the GUI directly starting from Tcl using the -p option and passing the Tcl file as an argument: vitis_hls -p  <file>.tcl
  • Interactive FIFO depth sizing in GUI
  • Constrained random testing for AXI interfaces now visible in the GUI

Versal Only Features

  • Vitis HLS now infers the dedicated single clock cycle accumulation for floating point (adder or multiplier) of the DSP58 block to implement efficient high throughput accumulation
  • Timing libraries updated for Versal production target devices

Vitis compiler & linker (v++)

  • Improved RTL-Kernel Integration:  Enhancements for packaging & integrating RTL IPs as kernels within Vitis applications, including support for user-managed RTL kernels (not controlled by XRT APIs) and improvements to IP Packager within Vivado to support this flow.
  • Multiple Implementation Strategies for Timing Closure: Vitis compiler & linker (v++) now supports launching & running multiple Vivado implementation strategies at the same time during hardware builds. This enables users to explore & assess all results and select the best strategy for final FPGA binary (xclbin) creation.

Versal Only Features

  • In 2020.2, as long as the hardware design stays the same, aiecompiler will only recompile and update to the software when AIE program is modified. The v++ linking stage is not re-run and it goes directly to the package step. This allows users to easily and quickly iterate on the AIE program after the HW has been fixed.
  • System Level template will be provided which includes AIE, PL and PS design files.
  • AIE tools features integrated into Vitis IDE, such as displaying pipeline information, storage view, parallel compilation etc.

Vitis IDE

  • Version Control for Vitis Projects: Integration with Git version control for Vitis Projects enables collaboration across multiple developers and teams.
  • Improvements to Project Hierarchy: Acceleration kernel and host applications are now separate projects under top-level System Project enabling a user to compile the host application and hardware kernels separately.
  • Improvements to Board Support Package (BSP) Build times: For platform projects with standalone domains, the Board Support Package (BSP) drivers compiles in parallel to speed up application build time.
  • Ease-of-Use for Host Application Debug: Processing System registers can be now be exported as a file from the Vitis GUI for debug.
  • Profiling System Projects: Top-level System Projects now offers more control over specifying profiling features via the Vitis GUI for the Vitis application acceleration flows.

View more: https://www.xilinx.com/products/design-tools/vitis/vitis-whats-new.html

Required system

Version 2020.2
Linux, 64-bit:

RHEL/CentOS 7.4, 7.5, 7.6, 7.7, 7.8, 8.1, 8.2
Ubuntu 16.04.5 LTS,16.04.6 LTS, 18.04.1 LTS, 18.04.2 LTS, 18.04.3 LTS, 18.04.4 LTS, 20.04 LTS
Amazon Linux 2 AL2 LTS

Version 2019.2

Supported Operating Systems

Xilinx supports the following operating systems on x86 and x86-64 processor architectures.

– Microsoft Windows 7 SP1 Professional (64-bit), English/Japanese *
– Microsoft Windows 10.0 1809 Update; 10.0 1903 Update (64-bit), English/Japanese
– Red Hat Enterprise Workstation/Server 7.4, 7.5, and 7.6 (64-bit)
– SUSE Linux Enterprise 12.4 (64-bit)
– CentOS 7.4, 7.5, and 7.6 (64-bit)
– Ubuntu Linux 16.04.5 LTS; 16.04.6 LTS; 18.04.1 LTS; 18.04.02 LTS (64-bit)
– Amazon Linux 2 LTS (64-bit)

* In alignment with Microsoft’s end of life support for Windows 7, Beginning with 2020.1 release, Xilinx will no longer support Windows 7.

2019.2 release of Vivado, Vitis, Model Composer & System Generator, will be the last release to support Windows 7.

In addition to this, beginning with 2020.1, Xilinx will also drop support for 32-bit HW server tool

Download Xilinx Vitis Core Development Kit / PetaLinux

The Vitis package also includes the Vivado and SDx suites

Download Xilinx Vitis Core Development Kit + PetaLinux 2021.1

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Download Xilinx Vitis Core Development Kit + PetaLinux 2020.2

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Download Xilinx Vitis Core Development Kit + PetaLinux 2019.2

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Password Extact file: 2020

Download guide

install Xilinx Vitis Core Development Kit / PetaLinux

see the readme.txt file

Chúng tôi không sử dụng linux vì vậy phần mềm chưa được test, và chúng tôi sẽ không hỗ trợ cài đặt

We do not use linux so the software has not been tested, and we do not support installation and troubleshooting